Date: October 30th, 2012 - November 5th, 2012
Group Number: May12-28/0 - Simultaneous Co-test of DAC ADC pairs
Group Adviser & Client: Dr. Chen
Accomplishments of Week: This week we focused our efforts strongly on characterizing the whole timing of the board. This ended when we had a timing design review on Friday with the group and our adviser. There were also efforts made to continue the design of the schematic and testing and verification of the timing of the board.
Plans for Coming Week: We will once again have our weekly meeting with our adviser on Friday. The input interface timing will be continued to be worked on and reviewed. The board schematic will be derived from the board timing. More design of the PCB schematic will be done along with timing simulations done in Verilog and Altair.
Pending Issues: Our issues right now are mostly dealing with our pushed timeline and strategies for verifying our design.
Individual Contributions:
Ben Magstadt: Worked on and presented on the board timing.
Luke Goetzke: Worked on and presented on the input interface timing.
Tao Chen: Worked on the layout & schematic of the PCB in Altium and did Verilog simulations of the board logic.
Group Number: May12-28/0 - Simultaneous Co-test of DAC ADC pairs
Group Adviser & Client: Dr. Chen
Accomplishments of Week: This week we focused our efforts strongly on characterizing the whole timing of the board. This ended when we had a timing design review on Friday with the group and our adviser. There were also efforts made to continue the design of the schematic and testing and verification of the timing of the board.
Plans for Coming Week: We will once again have our weekly meeting with our adviser on Friday. The input interface timing will be continued to be worked on and reviewed. The board schematic will be derived from the board timing. More design of the PCB schematic will be done along with timing simulations done in Verilog and Altair.
Pending Issues: Our issues right now are mostly dealing with our pushed timeline and strategies for verifying our design.
Individual Contributions:
Ben Magstadt: Worked on and presented on the board timing.
Luke Goetzke: Worked on and presented on the input interface timing.
Tao Chen: Worked on the layout & schematic of the PCB in Altium and did Verilog simulations of the board logic.