Date: January 22nd, 2012 - January 28th, 2012
Group Number: May12-28/0 - Simultaneous Co-test of DAC ADC pairs
Group Adviser & Client: Dr. Chen
Accomplishments of Week: We got the FPGA's memory interface to work, and started development of the verilog control code of the DAC and ADC. The new board layout was worked on, and finished and will be sent out for manufacturing by the end of the week.
Plans for Coming Week: Send new board off to be made by Advanced Circuits in Colorado. Continue work on Verilog code for the FPGA.
Pending Issues: Memory read/write issues on board to be finalized, and overall verilog code optimized.
Individual Contributions:
Ben Magstadt: Worked on FPGA memory interface (Verilog).
Luke Goetzke: Worked on Verilog interface that will handle the DAC and ADC.
Tao Chen: Worked on new layout of modified board.
Group Number: May12-28/0 - Simultaneous Co-test of DAC ADC pairs
Group Adviser & Client: Dr. Chen
Accomplishments of Week: We got the FPGA's memory interface to work, and started development of the verilog control code of the DAC and ADC. The new board layout was worked on, and finished and will be sent out for manufacturing by the end of the week.
Plans for Coming Week: Send new board off to be made by Advanced Circuits in Colorado. Continue work on Verilog code for the FPGA.
Pending Issues: Memory read/write issues on board to be finalized, and overall verilog code optimized.
Individual Contributions:
Ben Magstadt: Worked on FPGA memory interface (Verilog).
Luke Goetzke: Worked on Verilog interface that will handle the DAC and ADC.
Tao Chen: Worked on new layout of modified board.