Date: November 13th, 2012 - November 26th, 2012
Group Number: May12-28/0 - Simultaneous Co-test of DAC ADC pairs
Group Adviser & Client: Dr. Chen
Accomplishments of Week: This report combines the past two weeks as the previous week was Thanksgiving break. These two weeks were concentrated on finishing the design of the schematic. This has been finished with the most part with only a few small modifications going on. We had our official design review of the schematic on Monday.
Plans for Coming Week: We will once again have our weekly meeting with our adviser on Friday. This week will be dedicated to fixing the few existing problems in the schematic. It will also mark the beginning of our work on the layout of the PCB.
Pending Issues: Our issues right now are mostly dealing with our pushed timeline and strategies for verifying our design of the schematic and layout.
Individual Contributions:
Ben Magstadt: Worked on the schematic in the digital logic control, filter dimensions, and performed Verilog simulations of the entire board logic.
Luke Goetzke: Worked on the schematic in the IO, clocking, and buffers in filters.
Tao Chen: Completed the whole first draft of the schematic of the PCB in Altium.
Group Number: May12-28/0 - Simultaneous Co-test of DAC ADC pairs
Group Adviser & Client: Dr. Chen
Accomplishments of Week: This report combines the past two weeks as the previous week was Thanksgiving break. These two weeks were concentrated on finishing the design of the schematic. This has been finished with the most part with only a few small modifications going on. We had our official design review of the schematic on Monday.
Plans for Coming Week: We will once again have our weekly meeting with our adviser on Friday. This week will be dedicated to fixing the few existing problems in the schematic. It will also mark the beginning of our work on the layout of the PCB.
Pending Issues: Our issues right now are mostly dealing with our pushed timeline and strategies for verifying our design of the schematic and layout.
Individual Contributions:
Ben Magstadt: Worked on the schematic in the digital logic control, filter dimensions, and performed Verilog simulations of the entire board logic.
Luke Goetzke: Worked on the schematic in the IO, clocking, and buffers in filters.
Tao Chen: Completed the whole first draft of the schematic of the PCB in Altium.