Date: April 2nd, 2013 – April 30th, 2013
Group Number: May12-28/0 - Simultaneous Co-test of DAC ADC pairs
Group Adviser & Client: Dr. Chen
Accomplishments of Weeks: The issue to the output data was finally found to be caused from clock jitter. There weren’t function generators that were able to generate a pure enough clock to get rid of this problem. To get around this, the FPGA was able to generate a clock at the desired frequency using its internal clock generators. Once this was changed, our results seem to be what we were originally expecting. Our adviser and client is happy with the data that we are getting.
Plans for Coming Week: The only thing that is left is to create a new board and collect more data. We will create the new board with the solder reflow oven.
Pending Issues: There are no technical issues left. New boards and more data just need to be collected.
Individual Contributions:
Ben Magstadt: Debugged the board.
Luke Goetzke: Debugged the board.
Tao Chen: Debugged the board.
Group Number: May12-28/0 - Simultaneous Co-test of DAC ADC pairs
Group Adviser & Client: Dr. Chen
Accomplishments of Weeks: The issue to the output data was finally found to be caused from clock jitter. There weren’t function generators that were able to generate a pure enough clock to get rid of this problem. To get around this, the FPGA was able to generate a clock at the desired frequency using its internal clock generators. Once this was changed, our results seem to be what we were originally expecting. Our adviser and client is happy with the data that we are getting.
Plans for Coming Week: The only thing that is left is to create a new board and collect more data. We will create the new board with the solder reflow oven.
Pending Issues: There are no technical issues left. New boards and more data just need to be collected.
Individual Contributions:
Ben Magstadt: Debugged the board.
Luke Goetzke: Debugged the board.
Tao Chen: Debugged the board.