Senior Design - May13-280 Simultaneous Co-test of DAC ADC pairs
  • Home
  • Project Documents
  • Periodic Updates
    • October 2nd, 2012 - October 8th, 2012
    • October 9th, 2012 - October 15th, 2012
    • October 16th, 2012 - October 22nd, 2012
    • October 23rd, 2012 - October 29th, 2012
    • October 30th, 2012 - November 5th, 2012
    • November 6th, 2012 - November 12th, 2012
    • November 13th, 2012 - November 26th, 2012
    • November 27th, 2012 - December 3rd, 2012
    • December 4th, 2012 - January 14th, 2013
    • January 15th, 2013 - January 21st, 2013
    • January 22nd, 2013 - January 28th, 2013
    • January 29th, 2013 - February 25th, 2013
    • February 26th, 2013 - April 1st, 2013
    • April 2nd, 2013 - April 30th, 2013
    • May 1st, 2013 - May 10th, 2013
  • Project Background
  • Future Work
Date: April 2nd, 2013 – April 30th, 2013
Group Number: May12-28/0 - Simultaneous Co-test of DAC ADC pairs
Group Adviser & Client: Dr. Chen

Accomplishments of Weeks: The issue to the output data was finally found to be caused from clock jitter. There weren’t function generators that were able to generate a pure enough clock to get rid of this problem. To get around this, the FPGA was able to generate a clock at the desired frequency using its internal clock generators. Once this was changed, our results seem to be what we were originally expecting. Our adviser and client is happy with the data that we are getting.  

Plans for Coming Week:  The only thing that is left is to create a new board and collect more data. We will create the new board with the solder reflow oven.

Pending Issues:  There are no technical issues left. New boards and more data just need to be collected.

Individual Contributions:
Ben Magstadt: Debugged the board.
Luke Goetzke: Debugged the board.
Tao Chen: Debugged the board.

Create a free web site with Weebly