Date: November 6th, 2012 - November 12th, 2012
Group Number: May12-28/0 - Simultaneous Co-test of DAC ADC pairs
Group Adviser & Client: Dr. Chen
Accomplishments of Week: This week was focusing on integrating all of the past progresses into the schematic, as there is going to be a schematic review on Friday, November 16th. The input timing portion of the board was also reworked and more parts were found and included into the schematic.
Plans for Coming Week: We will once again have our weekly meeting with our adviser on Friday. This week will be dedicated to finalizing and verifying the schematic for our review on Friday. For this, most of the work will be done in Altair with some simulations being done in TINA Spice and Verilog for the logic portions.
Pending Issues: Our issues right now are mostly dealing with our pushed timeline and strategies for verifying our design.
Individual Contributions:
Ben Magstadt: Started working in Altair and put in more of the logic into the design.
Luke Goetzke: Worked on the input interface timing and schematic.
Tao Chen: Worked on the layout & schematic of the PCB in Altium and did Verilog simulations of the board logic.
Group Number: May12-28/0 - Simultaneous Co-test of DAC ADC pairs
Group Adviser & Client: Dr. Chen
Accomplishments of Week: This week was focusing on integrating all of the past progresses into the schematic, as there is going to be a schematic review on Friday, November 16th. The input timing portion of the board was also reworked and more parts were found and included into the schematic.
Plans for Coming Week: We will once again have our weekly meeting with our adviser on Friday. This week will be dedicated to finalizing and verifying the schematic for our review on Friday. For this, most of the work will be done in Altair with some simulations being done in TINA Spice and Verilog for the logic portions.
Pending Issues: Our issues right now are mostly dealing with our pushed timeline and strategies for verifying our design.
Individual Contributions:
Ben Magstadt: Started working in Altair and put in more of the logic into the design.
Luke Goetzke: Worked on the input interface timing and schematic.
Tao Chen: Worked on the layout & schematic of the PCB in Altium and did Verilog simulations of the board logic.