Date: October 23rd, 2012 - October 29nd, 2012
Group Number: May12-28/0 - Simultaneous Co-test of DAC ADC pairs
Group Adviser & Client: Dr. Chen
Accomplishments of Week: This week we worked on the design schematic. We worked heavily on the timing schematics and their associated circuits. We agreed upon various states of the board, and how we will communicate between them. The serial cable was verified to work for both input and output with proper circuitry.
Plans for Coming Week: We will once again have our weekly meeting with our adviser on Friday. The focus of this meeting is to hold the timing review, to ensure the completeness of our timing diagrams for all circuitry. Any issues that arise will be quickly addressed and modified for our design review two weeks after.
Pending Issues: Our timeline for publishing our results in an ITC paper has been moved up 6 weeks, with a deadline in early February.
Individual Contributions:
Ben Magstadt: Worked on the timing schematics further, agreed upon a 8 clk method for data input transfer to work with the serial cable.
Luke Goetzke: Verified the input scheme for the serial cable, and continued on the Labview code and started interfacing the communication method we developed.
Tao Chen: Worked on the layout & schematic of the PCB in Altair and TINA spice simulations for the DAC and ADC.
Group Number: May12-28/0 - Simultaneous Co-test of DAC ADC pairs
Group Adviser & Client: Dr. Chen
Accomplishments of Week: This week we worked on the design schematic. We worked heavily on the timing schematics and their associated circuits. We agreed upon various states of the board, and how we will communicate between them. The serial cable was verified to work for both input and output with proper circuitry.
Plans for Coming Week: We will once again have our weekly meeting with our adviser on Friday. The focus of this meeting is to hold the timing review, to ensure the completeness of our timing diagrams for all circuitry. Any issues that arise will be quickly addressed and modified for our design review two weeks after.
Pending Issues: Our timeline for publishing our results in an ITC paper has been moved up 6 weeks, with a deadline in early February.
Individual Contributions:
Ben Magstadt: Worked on the timing schematics further, agreed upon a 8 clk method for data input transfer to work with the serial cable.
Luke Goetzke: Verified the input scheme for the serial cable, and continued on the Labview code and started interfacing the communication method we developed.
Tao Chen: Worked on the layout & schematic of the PCB in Altair and TINA spice simulations for the DAC and ADC.