Date: October 2nd - October 8th
Group Number: May12-28/0 - Simultaneous Co-test of DAC ADC pairs
Group Adviser & Client: Dr. Chen
Accomplishments of Week: This week we continued work on the board design, as well as the timing scheme needed for the DAC, ADC and memory chips. After professional consultation, the board connectivity has been changed from a parallel port to a USB port. Current designs for this interface are in progress. This change will not affect any current designs in Labview or Altair.
Plans for Coming Week: We will once again have our weekly meeting with our adviser on Friday. Our goal for this week is to finalize the DAC-ADC portion of the board, and start to integrate the memory. The serial to parallel interface will also be a main focus. The DAC, ADC and memory clocking schemes will be blended together, and the USB interface will be resolved and initial designs completed.
Pending Issues: The complexity of a USB interface could cause a design issue. Labview needs to be installed in our lab because it will be needed there very soon.
Individual Contributions:
Ben Magstadt: Completed the individual timing schemes for the ADC, DAC, and two memory chips. Found a method for the overall
counters of the board on the negative edge of the clocks.
Luke Goetzke: Decided on the switch the interface to USB, sought out professional help, and started on integrated designs of the TUSB
chip.
Tao Chen: Worked on the layout & schematic of the PCB in Altium.
Group Number: May12-28/0 - Simultaneous Co-test of DAC ADC pairs
Group Adviser & Client: Dr. Chen
Accomplishments of Week: This week we continued work on the board design, as well as the timing scheme needed for the DAC, ADC and memory chips. After professional consultation, the board connectivity has been changed from a parallel port to a USB port. Current designs for this interface are in progress. This change will not affect any current designs in Labview or Altair.
Plans for Coming Week: We will once again have our weekly meeting with our adviser on Friday. Our goal for this week is to finalize the DAC-ADC portion of the board, and start to integrate the memory. The serial to parallel interface will also be a main focus. The DAC, ADC and memory clocking schemes will be blended together, and the USB interface will be resolved and initial designs completed.
Pending Issues: The complexity of a USB interface could cause a design issue. Labview needs to be installed in our lab because it will be needed there very soon.
Individual Contributions:
Ben Magstadt: Completed the individual timing schemes for the ADC, DAC, and two memory chips. Found a method for the overall
counters of the board on the negative edge of the clocks.
Luke Goetzke: Decided on the switch the interface to USB, sought out professional help, and started on integrated designs of the TUSB
chip.
Tao Chen: Worked on the layout & schematic of the PCB in Altium.