Date: January 29th, 2013 - February 25th, 2013
Group Number: May12-28/0 - Simultaneous Co-test of DAC ADC pairs
Group Adviser & Client: Dr. Chen
Accomplishments of Weeks: During the past month we have sent and received our completed manufactured board. We ordered and received most of our parts, and have begun soldering all components. Before we soldered we took a brief course to learn how to properly solder surface mount chips. Extensive work has been done on the memory Verilog/ FPGA interface code. There has been a very persistent error with the memory module read/write interface and we have done significant work to resolve this issue. We have contacted many individuals for help, and are currently working backward from the manufacturers read/write code. We are expected to have this major issue resolved in the coming week.
Plans for Coming Weeks: We will continue soldering parts to finish the first board, and arrange plans for a the board construction in a re-flow soldering oven. If soldering is finished we will begin initial debug of the board so it can be used for data collection. We hope to finish the memory module interface code for the FPGA. We will be having our second instructor meeting this week, in which the basis for our future industry presentation will be presented.
Pending Issues: Memory read/write issues on board to be finalized.
Individual Contributions:
Ben Magstadt: Worked extensively on FPGA memory interface (Verilog). Continued revision on Matlab code for testing algorithm.
Luke Goetzke: Worked on Verilog interface that will handle the DAC and ADC. Soldering. Created presentation for instructor meeting.
Tao Chen: Communicated / coordinated order/shipping of board. Soldering.
Group Number: May12-28/0 - Simultaneous Co-test of DAC ADC pairs
Group Adviser & Client: Dr. Chen
Accomplishments of Weeks: During the past month we have sent and received our completed manufactured board. We ordered and received most of our parts, and have begun soldering all components. Before we soldered we took a brief course to learn how to properly solder surface mount chips. Extensive work has been done on the memory Verilog/ FPGA interface code. There has been a very persistent error with the memory module read/write interface and we have done significant work to resolve this issue. We have contacted many individuals for help, and are currently working backward from the manufacturers read/write code. We are expected to have this major issue resolved in the coming week.
Plans for Coming Weeks: We will continue soldering parts to finish the first board, and arrange plans for a the board construction in a re-flow soldering oven. If soldering is finished we will begin initial debug of the board so it can be used for data collection. We hope to finish the memory module interface code for the FPGA. We will be having our second instructor meeting this week, in which the basis for our future industry presentation will be presented.
Pending Issues: Memory read/write issues on board to be finalized.
Individual Contributions:
Ben Magstadt: Worked extensively on FPGA memory interface (Verilog). Continued revision on Matlab code for testing algorithm.
Luke Goetzke: Worked on Verilog interface that will handle the DAC and ADC. Soldering. Created presentation for instructor meeting.
Tao Chen: Communicated / coordinated order/shipping of board. Soldering.