Date: October 16th, 2012 - October 22nd, 2012
Group Number: May12-28/0 - Simultaneous Co-test of DAC ADC pairs
Group Adviser & Client: Dr. Chen
Accomplishments of Week: This week we continued work on the board design. We verified that the serial interface will work well for our needs through simulation with Labview, and verified that the baud rate can be synchronized on the receiving end. The schematics at the receiving end of the serial cable was designed to allow easy board set up. The maximum data transfer frequency per byte was decided as 10kHz, since the maximum baud for our serial cable is 115200bps. The Labview code was then modified to account for the serial cable. The timing diagrams were modified to match the new serial timing interface, and the timing schematics were generated for the first half (input) side of the board. We found that we cannot fully simulate our board, since spice models do not exist for our DAC and ADC. We decided that we will have hold a timing review on November 9th, and the design review on November 16th.
Plans for Coming Week: We will once again have our weekly meeting with our adviser on Friday. The Labview code will be worked on more for the output schemes with board data and board setup bytes. The Serial cable design and schematics will be worked on for input data from the board. The timing diagrams and schematics will be continued.
Pending Issues: We need to hold a design and timing review, and each need to verify Ben's work on the timing diagrams. The serial cable is very limited as to it's speed overall slowly down the board design, however this may be needed for it's ease of use. Full board simulation cannot be done, since DAC and ADC spice models do not exist for our needs; simulation we need to be elsewhere.
Individual Contributions:
Ben Magstadt: Completed the board timing diagrams to match the serial interface, and created timing schematics for the input side of the board.
Luke Goetzke: Concluded that the Serial interface will work well enough for our solution through bench verification, proceeded with the Labview design associated with the serial interface, designed the board receiving end for the serial line.
Tao Chen: Worked on the layout & schematic of the PCB in Altium.
Group Number: May12-28/0 - Simultaneous Co-test of DAC ADC pairs
Group Adviser & Client: Dr. Chen
Accomplishments of Week: This week we continued work on the board design. We verified that the serial interface will work well for our needs through simulation with Labview, and verified that the baud rate can be synchronized on the receiving end. The schematics at the receiving end of the serial cable was designed to allow easy board set up. The maximum data transfer frequency per byte was decided as 10kHz, since the maximum baud for our serial cable is 115200bps. The Labview code was then modified to account for the serial cable. The timing diagrams were modified to match the new serial timing interface, and the timing schematics were generated for the first half (input) side of the board. We found that we cannot fully simulate our board, since spice models do not exist for our DAC and ADC. We decided that we will have hold a timing review on November 9th, and the design review on November 16th.
Plans for Coming Week: We will once again have our weekly meeting with our adviser on Friday. The Labview code will be worked on more for the output schemes with board data and board setup bytes. The Serial cable design and schematics will be worked on for input data from the board. The timing diagrams and schematics will be continued.
Pending Issues: We need to hold a design and timing review, and each need to verify Ben's work on the timing diagrams. The serial cable is very limited as to it's speed overall slowly down the board design, however this may be needed for it's ease of use. Full board simulation cannot be done, since DAC and ADC spice models do not exist for our needs; simulation we need to be elsewhere.
Individual Contributions:
Ben Magstadt: Completed the board timing diagrams to match the serial interface, and created timing schematics for the input side of the board.
Luke Goetzke: Concluded that the Serial interface will work well enough for our solution through bench verification, proceeded with the Labview design associated with the serial interface, designed the board receiving end for the serial line.
Tao Chen: Worked on the layout & schematic of the PCB in Altium.